A circuit diagram that controls the charge and discharge of the absorption capacitance. ,
(a) the principle circuit; (b) a practical circuit controlling the charging and discharging of the absorption capacitor.
The pulse from the PWM integrated controller makes it work on / off. In order to make the VF2 / VF1 time reverse, a two-way delay circuit S1 is added. It is now assumed that the VF1 is the cut-off state and the VF2 is the conduction state, which absorbs the capacitor Cr to charge to the drain source voltage of the VF1, and thus also absorbs the surge voltage added to the VF1. The VF2 cutoff after the delay time determined by the delay circuit, but at this time, the voltage at both ends of the Cr is equal to the voltage added to the VF1, so the switching mode of the zero voltage and zero current switching device is made.
The two side diode VD2 current drops to zero, and the transformer has no excitation power. At this time, the return voltage of the main winding N1 induction turns to zero, and the absorption capacitance C1, which is higher than the voltage on the C1, reversely discharge to a primary winding N1, so that the discharge current is circulated through the parasitic diode of the VF2 (the dotted line). When the Cr discharge begins, the VF2 must be cut off. Because of the Cr discharge, the capacitance Cr resonates with the inductance Lp of the primary winding.
If VF2 is in conduction state, the resonance will continue to attenuate oscillation, but when the VF2 is cut off, the oscillation will stop when the voltage of capacitor Cr ends to zero. If Cr stops resonance, the smaller capacitance capacitance of VF1 and VF2 will continue to generate shorter period resonance. When VF1 is turned on again, the small capacitor discharge current flows through the VF1 itself and consumes it. When the VF1 is on, the voltage of the small capacity capacitor charge varies with the passing time, but the voltage of the Cr is reduced to the lowest voltage. Therefore, the loss of the Cr can be reduced. That is to say, even if the capacitor with large capacitance is used, the loss of Cr will not increase.
The general M0S FET parasitic diode recovery characteristic is not suitable for high frequency. Therefore, the low consumption diode is added as the capacitive discharge diode to make all the discharge current flow through the diode VD1. In the VF2 loop, the pressure drop of the reverse blocking diode VD2. reverse blocking diode VD2 is larger than the positive voltage drop of the VD1, so the selection is selected. Using the Schottky diode (SBD). In addition, the bi-directional delay element should adopt a saturable reactor, the delay element and the input capacitance of YF2 decide the time delay time. When a long time delay is needed, the capacitor can be added at the gate. When the output current is reduced, the conduction time of VF1 becomes shorter. If the conduction time is shorter than the delay time, the VF2 is connected after the VF1 cut-off, so the waveform of the VF1 drain source voltage UDS deviates from the normal waveform, and the power consumption is slightly increased. In order to reduce the minimum output current, the delay time is very short, so the capacitor Cr can not be fully and effectively utilized. Here, as a general goal, the minimum output current is set to 2% to 3% of the maximum output current.